Minimizing defects during wafer processing will continue to be a critical path to attaining cost effective manufacturing of advanced semiconductor devices. Hard particles can block etch processes causing electrical “open” or “short” in the circuit. In lesser size and if lucky with the location on the device, the hard particle may only create fatal perturbations in the active features' critical dimension (line/space or contact hole)
The required gate level defect density for 15 nm gate technology is going to be approximately 0.01/cm**2 at 10 nm in size per the International Technology Roadmap for Semiconductors (ITRS) 2005 roadmap. Prior art thermal processing procedures are not adequate to meet these requirements, and it is anticipated that an improved thermal processing system and associated procedures will be required to meet the future device defect densities.